SAN JOSE — A consortium of chip-equipment makers here today announced a major deal with Ace Semiconductor to help set up the world's first wafer-level packaging production line in China. Under the ...

This study investigates creation of 1.0µm RDL structures by a damascene process utilizing a photosensitive permanent dielectric material. The advantage of the photosensitive dielectric approach is ...

Austin, March 30, 2026 (GLOBE NEWSWIRE)-- Wafer Level Packaging Market Size & Growth Outlook: According to the SNS Insider, “The Wafer Level Packaging Market Size was valued at USD 9.73 Billion in ...

Get ready for wafer-level packaging. The Semiconductor Equipment Consortium for Advanced Packaging (SECAP) said at Semicon West in San Francisco this week that it will install a complete 300mm line ...

Dr. Navid Asadi’s group takes a look at wafer to panel level chip packaging. This is the six of a mutlipart series on chip packaging technologies. Navid Asadi is an assistant professor in the ...

Samsung Electronics has stepped up its deployment in the fan-out (FO) wafer-level packaging segment with plans to set up related production lines in Japan, according to industry sources. Samsung has ...

Fraunhofer’s panel experts dig into why this approach is needed and where the challenges are to making it work. Semiconductor Engineering sat down to discuss panel-level fan-out packaging technology ...

The facility will sit on a 230,000 sqm (2.48 million sq ft) parcel of land within the Cheongju Technopolis Industrial Complex. According to SK Hynix, it will feature three floors of wafer-level ...

ASE Technology is committing $200 million to test a new method of chip packaging that replaces traditional round wafers with ...

Wedbush connects a routine financing deal to a much bigger AI chip problem brewing for 2028 and beyond.