EDN

Advancing FPGA design flows using Chronology’s TimingDesigner

When combined with advances in FPGA technologies that ease complex interface design efforts, Chronology's TimingDesigner can simplify design issues and provide advanced accurate control of high-speed ...
Semiconductor Engineering

FPGA Design Tradeoffs Getting Tougher

FPGAs are getting larger, more complex, and significantly harder to verify and debug. In the past, FPGAs were considered a relatively quick and simple way to get to market before committing to the ...
EDN

How to design FPGA-based advanced PCI Express endpoint solutions

Currently dominating the desktop PC motherboard and graphics markets, the PCI Express protocol is poised to supplant PCI and PCI-X interface as the dominant high-bandwidth interconnect for the server, ...
Circuit Digest

Soan Papdi FPGA Development Board Is Set to Launch on Crowd Supply

Ashok Tinkering Labs, based in Ahmedabad, India, is preparing to launch Soan Papdi, an FPGA development board aimed at ...
Semiconductor Engineering

Challenges In Using HLS For FPGA Design

High-level synthesis (HLS) tools, which transform C/C++ source code to Verilog/VHDL, have been commercially available for over 15 years. HLS tools from FPGA vendors and EDA companies promise improved ...
Business Wire

PRO DESIGN Unveils New Xilinx® Virtex® UltraScale+™ VU19P-Based Product Family of Prototyping Platforms

MUNICH--(BUSINESS WIRE)--PRO DESIGN, veteran in the E²MS industry and leading supplier of high-speed ASIC and SoC verification platforms, launches today its new proFPGA UNO, DUO and QUAD systems based ...
Hackaday

FPGA Design From Top To Bottom

[Roland Lutz] gave a talk about FPGA design using the free tools for Lattice devices at the MetaRheinMainChaosDays conference this year. You can see the video below. It’s a great introduction to FPGAs ...